Introduction to SV

SystemVerilog

SystemVerilog is a High-level Verification Language (HVL), which is a superset of Verilog HDL. SystemVerilog adds extensive enhancements to Verilog-2001 IEEE standards. SV includes features from languages such as Verilog, C, C++, Vera. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog has become an IEEE standard P1800-2005.

Some of the new features that SystemVerilog supports are:
1. Dynamic datatypes like Dynamic Queues and Dynamic Arrays.
2. New operators and built-in methods.
3. Classes for Object-Oriented Programming.
4. Mailboxes, Semaphores and Events.
5. Constrained Randomization methods.
6. Assertions
7. Coverage
8. Interfaces
9. Program blocks and Clocking blocks
10. Direct Programming Interface (DPI)


* Need for SystemVerilog?
          - As the designs are getting more and more complex, verification of such design needs a language that makes it easy to implement ways to simplify the verification process.
 
          - SystemVerilog is extremely scalable, in the sense that it can be used both by Hardware Designers and Verification engineers.

WELCOME

Hello Everyone,

Welcome to my blog!

I am creating this blog about SystemVerilog, with examples, to help you learn the language constructs and their implementation in a real world example.

The pre-requisite for learning SystemVerilog language is the knowledge of Verilog language and the Object Oriented Programming concepts (OOPs).

The link for SystemVerilog Language Reference Manual (LRM) is also posted below for your reference:

http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf

Hope this blog serves you well and answers your questions/doubts to the point.

Any feedback/corrections regarding the posts are welcomed and appreciated. Your feedback will only help others referring to this blog.